CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies (Repost)
CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies: Process-Aware SRAM Design and Test
Publisher: Springer | pages: 212 | 2008 | ISBN: 1402083629 | PDF | 10,6 mb
Publisher: Springer | pages: 212 | 2008 | ISBN: 1402083629 | PDF | 10,6 mb
As technology scales into nano-meter region, design and test of Static Random Access Memories (SRAMs) becomes a highly complex task. Process disturbances and various defect mechanisms contribute to the increasing number of unstable SRAM cells with parametric sensitivity. Growing sizes of SRAM arrays increase the likelihood of cells with marginal stability and pose strict constraints on transistor parameters distributions.