Designing Risc-V Cpu In Verilog And Its Fpga Implementation

Understanding RISC-V ISA (RV32I), Verilog implementation of custom RISC-V CPU, LED GPIO, UART and porting to FPGA

What you'll learn

Able to develop and demonstrate a working RISC-V processor core on an FPGA, capable of executing basic programs and interacting with peripherals

To demonstrate proficiency in using hardware description languages (Verilog) and FPGA synthesis tools

Students will be able to integrate a RISC-V core with memory and peripherals, debug hardware and software, and analyze system performance on an FPGA

To be familiar with real-world application of RISC-V architecture using your own CPU.

Requirements

Essential: Basics of Digital Electronics and basic idea about C programming.

Description

This comprehensive course, "Designing RISC-V CPU in Verilog and its FPGA Implementation",  offers a deep dive into the fascinating world of custom processor design, focusing on the open-source RISC-V instruction set architecture (ISA). Participants will gain hands-on experience in architecting, describing, and implementing a functional RISC-V CPU core using the Verilog Hardware Description Language (HDL) and deploying it on Field-Programmable Gate Arrays (FPGAs).The course begins by establishing a strong foundation in digital logic design principles and reviewing essential Verilog constructs relevant to complex digital systems. We will then introduce the RISC-V ISA (RV-32I), exploring its modularity, extensibility, and key instruction formats. Students will learn how to interpret the ISA specifications and translate them into hardware logic.This course also provides step-by-step guidelines to set up the RISC-V toolchain, including assembler and GCC compiler, to write an embedded-C programme and compile it to Hex code, which will be loaded into an FPGA to access peripherals such as LEDs and UART.A significant portion of the course is dedicated to the step-by-step design of a single-cycle RISC-V CPU. Topics covered will include:Instruction Fetch Unit: Designing the program counter and instruction memory interface.Decode Unit: Implementing instruction decoding logic, register file access, and control signal generation.Execute Unit: Building the Arithmetic Logic Unit (ALU) and handling data path operations.Memory Unit: Designing data memory interfaces for load and store operations.Write-back Unit: Updating the register file with computed results.Control Unit: Developing the finite state machine (FSM) or combinational logic to orchestrate CPU operations.Emphasis will be placed on best practices in Verilog coding for synthesis, including modular design, parameterization, and robust test bench creation. Students will learn how to simulate their Verilog designs using industry-standard tools to verify functional correctness at each stage of the CPU development.The latter part of the course focuses on the practical aspects of FPGA implementation. Participants will learn how to:Synthesize their Verilog CPU design into a gate-level netlist.Perform Place and Route to map the design onto specific FPGA resources.Generate bitstreams for programming the FPGA.Debug and test their implemented CPU on actual FPGA hardware, often by integrating peripherals like LEDs and UART for basic I/O and interaction.By the end of this course, students will not only have a thorough understanding of RISC-V architecture and CPU design principles but also possess the practical skills to bring a complex digital design from concept to a working hardware implementation on an FPGA. This knowledge is invaluable for careers in embedded systems, custom silicon design, hardware acceleration, and research in computer architecture. A basic understanding of digital logic and Verilog is recommended.Note: Only Base Integer Instruction (RV32I) is discussed and implemented in Verilog and FPGA. Also, you need one FPGA board for the hardware implementation of CPU. A basic FPGA board, such as Tang-9K, is sufficient for this.

Overview

Section 1: Introduction

Lecture 1 Introduction

Section 2: RV32I- The Base Integer Instructions

Lecture 2 RV32I- Introduction and Registers bank

Lecture 3 Register type (R-type) instruction format

Lecture 4 Other instruction format of RISC-V

Lecture 5 Writing assembly language code

Lecture 6 Lab session: sample assembly programme

Section 3: Beginner's guide to Verilog HDL

Lecture 7 Introduction to Verilog HDL

Lecture 8 Modules and data types

Lecture 9 Verilog operators

Lecture 10 Bit extension in Verilog

Lecture 11 Number Representation in Verilog

Lecture 12 Initial and Always Block

Lecture 13 Modelling styles in Verilog

Lecture 14 Sample Verilog Code Explanations

Lecture 15 Lab session: Setting up Tools and IDE

Lecture 16 Lab: Simulation of Full adder

Lecture 17 Lab: Simulation of Counter

Section 4: Design of Program memory unit

Lecture 18 Design of Program Memory

Lecture 19 Testing the program memory

Section 5: Design of RISC-V CPU with RV32I ISA supported instructions

Lecture 20 Understanding instruction set before designing CPU

Lecture 21 Input, Output and temporary wires and registers

Lecture 22 Fetching information from memory data

Lecture 23 Design of ALU

Lecture 24 Design of state machine to control operation

Lecture 25 Register Write back

Lecture 26 Connecting CPU with Program Memory

Lecture 27 Testing the CPU with R-type and I-type instructions

Lecture 28 Adding Branch type instructions

Lecture 29 Testing Branch type instructions

Lecture 30 Implementing Load, Store and other instructions

Lecture 31 Testing Load, Store and other instructions

Lecture 32 Configuring RISC-V GCC toolchain and installing

Section 6: Adding Peripheral to RISC-V core and FPGA implementation

Lecture 33 Adding LEDs to RISC-V core

Lecture 34 Writing C code in RISC-V GCC and compiling and running testbench

Lecture 35 FPGA implementation of LED GPIO

Lecture 36 Adding UART Transmitter to Design

Lecture 37 Testing UART Transmitter on FPGA

Lecture 38 Adding UART Receiver in the Design

Lecture 39 FPGA implementation and testing of UART receiver

Lecture 40 Combining all GPIO together to make a SoC

Lecture 41 Tips and Tricks for Xilinx AMD FPGA using Vivado

This course is primarily designed for electrical , electronics and computer engineering students, particularly for undergraduate or postgraduate . These learners are expected to have a foundational understanding of digital logic design, computer architecture, and basic programming concepts. Furthermore, it caters to practicing engineers and hardware enthusiasts who wish to deepen their knowledge in custom CPU design, embedded systems, and FPGA development. Professionals working with ASICs, SoCs, or embedded systems who want to explore open-source CPU architectures and their practical implementation will find this course highly beneficial. A strong interest in hardware description languages (specifically Verilog), digital circuit synthesis, and a desire to build and test a functional CPU from the ground up are crucial for prospective learners. While some prior exposure to Verilog helpful, the course will also accommodate those willing to learn these languages within the context of CPU design. Ultimately, the intended learner is someone keen on hands-on hardware development and the intricate details of modern CPU architectures.