Vlsi Dft Basics: From Industry Perspective

The purpose of DFT testing in VLSI along with industry standard DFT implementation flows

What you'll learn

The purpose of DFT testing in VLSI and its role in reliable chip manufacturing

The chip design flow and how DFT integrates into chip design flow

Common manufacturing defects and fault models (stuck-at, transition, IDDQ, path delay)

Introduction to core DFT techniques including SCAN, MBIST, and Boundary Scan

How analog IPs are tested — a topic rarely covered in other courses

Never taught before industry-standard DFT implementation flow used in real chip projects

Requirements

Basic digital logic design knowledge (logic gates, flip-flops, combinational vs. sequential circuits)

Familiarity with HDL (Verilog or VHDL) at an introductory level

Basic awareness of the VLSI design flow (RTL to GDSII)

General understanding of semiconductor basics (what is a chip, role of transistors, CMOS)

Comfortable with timing concepts such as setup/hold, clock, and reset

Description

VLSI DFT Basics: From Industry PerspectiveUnlock the world of Design-for-Test (DFT) with this industry-oriented course designed for engineers, graduate students, and VLSI enthusiasts. DFT is a critical part of modern chip design, ensuring that your silicon is manufacturable, reliable, and testable.In this course, you’ll learn the concepts and methods used by top semiconductor companies, presented in simple, easy-to-understand language. Unlike traditional courses, this course also covers analog IP testing and DFT implementation flows—a topic often missing in standard DFT training.You’ll gain hands-on understanding of:Why testing is crucial and the goals it servesThe types of manufacturing defects and fault modelsCore DFT methods including SCAN, MBIST, and boundary scanHow DFT is integrated into the industry-standard chip design flowWhether you’re a fresh graduate, RTL/backend engineer, verification engineer, or aspiring DFT professional, this condensed curriculum delivers months of industry knowledge in just a few hours.By the end of this course, you’ll be ready to understand basics of DFT and DFT implementation flows used in industry in real-world chip designs.This course was designed personally by me as it took me months to understand about VLSI DFT and went through so many books, trainings, user guides, and a lot more. I have condenesed all of my months of learning into this short course, which I also present in chip companies.

Overview

Section 1: Introduction

Lecture 1 Introduction

Section 2: The Purpose of Testing (Why?)

Lecture 2 Chip Design Flow-RTL to GDSII

Lecture 3 Purpose of Testing

Lecture 4 Types of Testing

Section 3: The Target of Testing (What?)

Lecture 5 Manufacturing Defects

Lecture 6 Fault Modeling and Types

Lecture 7 Stuck-at Fault Model

Lecture 8 Transition Fault Model

Lecture 9 IDDQ Fault Model

Lecture 10 Path Delay Fault Model

Lecture 11 Cell-Aware Fault Model

Section 4: The Basics of Testing Methods (How?)

Lecture 12 Introduction to Basics of Testing Methods Section

Lecture 13 Introduction of Basics of Testing Methods

Lecture 14 Building Blocks of Chip

Lecture 15 Memory BIST (MBIST)

Lecture 16 Boundary Scan Diagnosis (BSD)

Lecture 17 SCAN

Lecture 18 Analog IPs Testing

Section 5: Basic DFT Implementation Flows used in Industry

Lecture 19 Basic DFT Implementation Flows used in Industry

Lecture 20 Basic SCAN Insertion Flow

Lecture 21 MBIST Insertion Flow

Lecture 22 BSD Insertion Flow

Lecture 23 Analog IP Test Mode Insertion Flow

Lecture 24 Different Tools Usage in DFT

Section 6: Conclusion

Lecture 25 Conclusion

Section 7: Test your knowledge

Undergraduates, fresh graduates or early-career engineers looking to build a foundation in DFT,RTL, synthesis, and physical design (place & route) engineers seeking DFT awareness,DFT engineers and flow developers aiming to strengthen foundational knowledge,Graduate students aspiring to build a career in the DFT domain